TS-MAC-XM-UT4【PDF 59/66 页】SITE LICENSE ETH MAC TRI-SPD XP

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Chapter 6:

Core Validation

The Lattice TSMAC IP core has been validated through interoperability tests with several external PHY devices. An

external ethernet protocol generator/analyzer, such as the Spirent Smartbits tester, was used to drive/monitor eth-

ernet traffic through the IP core test circuit.

The IP core was also tested in a real ethernet network environment. Refer to the following Lattice interoperability

Technical Notes and documents:

? TN1196 - LatticeECP3 Marvell 1 GbE (1000BASE-X) Physical/MAC Layer Interoperability

? TN1197 - LatticeECP3/Marvell SGMII Physical/MAC Layer Interoperability

? LatticeMico32 Tri-Speed Ethernet MAC Demo web site ?

( http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/mico32trispeedethernetmac.cfm )

? LatticeMico32 Ethernet Gigabit MAC Demo web site: ?

( http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/mico32ethernetgigabitmacd.cfm )

IPUG51_03.0, December 2010

59

Tri-Speed Ethernet MAC User’s Guide

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